RTL Design Engineer / Digital lead Engineer - IP or SOC
- Responsible for design and integration of ARM based processor SOC and subsystem.
- Solid experience in digital VLSI design.
- Good understanding of Multi-processor and cache designs.
- Hands on coding experience in Verilog/VHDL.
- Familiarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols.
- Has good knowledge on various tools viz Spyglass, 0-in, DC-Compiler, Prime time,
PTPX, Power-Artist,LEC etc.
- Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus.