Senior Physical Design Engineer - IC

4+ yearsBangalore
Job Description
  • Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation.
  • Block level implementation from netlist to GDS.
  • Handling timing closure of high frequency blocks.
  • Handling blocks of high instance counts 1M instance and above.
  • Expertise in signoff closure Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level.
  • Understanding constraints and fixing techniques.
  • Understanding SI prevention , fixing methodology and implementation.
  • Proficient in layout edit techniques.
  • Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set.
  • Experience in Design Automation and UNIX system.
  • Experience in Tcl/Tk, PERL is a plus.